View MT9J003D00STMUC2CBC1-200_8320866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mt9j003: 1/2.3-inch 10 mp cmos digital image sensor features mt9j003-ds rev. e 5/15 en 1 ?semiconductor components industries, llc,2015 1/2.3-inch 10 mp cmos digital image sensor mt9j003 datasheet, rev. e for the latest datasheet, please visit www.onsemi.com features ? 1080p digital video mode ? simple two-wire serial interface ? auto black level calibration ? support for external mechanical shutter ? support for external led or xenon flash ? high frame rate preview mode with arbitrary down- size scaling from maximum resolution ? programmable controls: gain , horizontal and vertical blanking, auto black level offset correction, frame size/rate, exposure, left?rig ht and top?bottom image reversal, window size, and panning ? data interfaces: parallel or fo ur-lane serial high-speed pixel interface (hispi) differential signaling (sub- lv ds ) ? on-die phase-locked loop (pll) oscillator ? bayer pattern downsize scaler ? integrated position-based color and lens shading correction ? one-time programmable memory (otpm) for storing module information applications ? digital video cameras ? digital still cameras general description the on semiconductor mt9j003 is a 1/2.3-inch cmos active-pixel digital imaging se nsor with an active pixel array of 3856h x 2764v including border pixels. it can support 10 megapixel (3664h x 2748v) digital still images and a 1080p (3840h x 2160v) digital video mode. it incorporates sophisticated on-chip camera functions such as windowing, mirroring, column and row skip modes, and snapshot mode. it is programma- ble through a simple two-wire serial interface and has very low power consumption. table 1: key performance parameters parameter value optical format 1/2.3-inch (4:3) active imager size 6.440 mm (h) x 4.616 mm (v), 7.923 mm diagonal (entire sensor) 6.119 mm (h) x 4.589 mm (v), 7.649 mm diagonal (still mode) 6.413 mm (h) x 3.607 mm (v), 7.358 mm diagonal (video mode) active pixels 3856h x 2764v (entire sensor) 3664h x 2748v (4:3, still mode) 3840h x 2160v (16:9, video mode) pixel size 1.67 x 1.67 ? m chief ray angle 0, 13.4 color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) with global reset release (grr) input clock frequency 6C48 mhz maxi- mum data rate parallel 80 mp/s at 80 mhz pixclk hispi (4-lane) 2.8 gbps frame rate still mode, 4:3 (3664h x 2748v) programmable up to 15 fps serial i/f, 7.5 fps parallel i/f preview mode vga 30 fps with binning 60 fps with skip2bin2 1080p mode (1920h x 1080v) 60 fps using hispi i/f 30 fps using parallel i/f adc resolution 12-bit, on-die responsivity 0.31 v/lux-sec (550nm) dynamic range 65.2 db snr max 34 db supply voltage i/o digital 1.7C1.9 v (1.8 v nominal) or 2.4C3.1 v (2.8 v nominal) digital 1.7C1.9 v (1.8 v nominal) analog 2.4C3.1 v (2.8 v nominal) slvs i/o 0.4 - 0.8 v (0.4 or 0.8 v nominal) power con- sump- tion still mode at 15 fps w/ serial i/f 638mw still mode at 7.5 fps w/ parallel i/f 388mw preview 250mw low power vga standby 500 ? w (typical, extclk disabled) package 48-pin ilcc (10mm x 10mm) bare die, 48pin tiny plcc (12mm x 12mm) operating temperature C30c to +70c (at junction)
mt9j003-ds rev. e 5/15 en 2 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9J003D00STMUC2CBC1-200 10 mp 1" cis die sales, 200 ? m thickness mt9j003i12stcu-dp 10 mp 1/2.3" cis dry pack with protective film mt9j003i12stcu-dr 10 mp 1/2.3" cis dry pack without protective film mt9j003i12stcv2-dp 10 mp 1/2.3" cis dry pack with protective film mt9j003i12stcv2-tp 10 mp 1/2.3" cis tape & reel with protective film mt9j003i12stmu-dp 10 mp 1/2.3" cis dry pack with protective film
mt9j003-ds rev. e 5/15 en 3 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 programming restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 control of the signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 sensor readout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 sensor core digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
mt9j003-ds rev. e 5/15 en 4 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: hispi package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: 48-pin ilcc parallel package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: hispi transmitter and receiver in terface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: block diagram of dll ti ming adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: delaying the clock_lane with re spect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: delaying data_lane with respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 12: steaming vs. packetized transmis sion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13: spatial illustration of image readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 14: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: row timing and fv/lv signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 16: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 17: single read from current locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 18: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 19: sequential read, start from current location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 20: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 22: effect of limiter on the data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 23: timing of data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 24: mt9j003 system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 25: clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: sequence for programming the mt9j003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 27: effect of horizontal mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 28: effect of vertical flip on re adout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 29: pixel array readout without subs ampling and with 2x2 skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 30: combinations of pixel skipping in the mt9j003 sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 31: pixel binning and summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 32: pixel skipping combined with summing or binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 33: xenon flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 34: led flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 35: led flash enabled following forc ed restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 36: overview of global reset sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 37: entering and leaving a global re set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 38: controlling the reset and integration phases of the gl obal reset sequence . . . . . . . . . . . . . . . . . . . .53 figure 39: control of the electromechanica l shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 40: controlling the shutter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 41: using flash with global reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 42: global reset bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 43: entering soft standby during a global reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 44: test cursor behavior with image orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 45: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 46: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 47: hard standby and hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 48: soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 49: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 50: two-wire serial bus timing para meters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 51: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 52: hispi eye diagram for both clock and data signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 53: hispi skew between data signals within the phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 54: 48-pin ilcc package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 55: 48-pin tplcc package outline draw ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
mt9j003-ds rev. e 5/15 en 5 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: row timing with hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 5: row timing with parallel interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 6: row timing with parallel interfac e using low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7: register settings for common reso lutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 8: definitions for programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 9: output enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 10: configuration of the pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 11: reset_bar and pll in system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 12: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 13: streaming/standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 14: trigger control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 15: subsampling combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 16: minimum row time and blanking numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 17: minimum frame time and blanking numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 18: fine_integration_time limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 19: fine_correction values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 20: recommended gain stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 21: test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 22: hispi test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 23: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 24: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 25: cra (13.4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 26: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 27: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 28: parallel interface configured to use low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 29: two-wire serial register interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 30: two-wire serial register interface timing specificatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 31: i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 32: i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 33: hispi rise and fall times at 480 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 34: hispi rise and fall times at 360 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 35: channel, phy and intra-phy skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 36: clock dll steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 37: data dll steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 38: 48-pin tplcc pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
mt9j003-ds rev. e 5/15 en 6 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor general description general description the mt9j003 digital image sensor features on semiconductor?s breakthrough low-noise cmos imaging technology that achieves ne ar-ccd image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. when operated in its default 4:3 still-mode, th e sensor generates a full resolution image at 15 frames per second (fps) using the hisp i serial interface. an on-chip analog-to- digital converter (adc) generates a 12-bit value for each pixel. functional overview the mt9j003 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 80 mp/s, corresponding to a pixel clock rate of 80 mhz. a block diagram of the sensor is shown in figure 1. figure 1: block diagram the core of the sensor is a 10mp active-pix el array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chai n (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the pixel array contains optically active and light-shielded (?dark?) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (?black level? control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. active-pixel sensor (aps) array analog processing adc scaler limiter shading correction fifo timing control control registers data out two-wire serial interface sync signals
mt9j003-ds rev. e 5/15 en 7 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor functional overview the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. the control registers, timing and control, and digital processing functions shown in figure 1 on page 6 are partitioned into three logical parts: ? a sensor core that provides array control and data path corrections. the output of the sensor core is a 12-bit parallel pixel data stream qualified by an output data clock (pixclk), together with line_valid (lv) and frame_valid (fv) signals or a 4-lane serial high-speed pixel interface (hispi). ? a digital shading correction block to comp ensate for color/brightness shading intro- duced by the lens or chief ray angle (cra) curve mismatch. ? additional functionality is provided. this includes a horizontal and vertical image scaler, a limiter, a data compressor, an output fifo, and a serializer. the output fifo is present to prevent data bursts by keeping the data rate continuous. programmable slew rates are al so available to reduce the e ffect of electromagnetic inter- ference from the output interface. a flash output signal is provided to allow an external xenon or led light source to synchronize with the sensor exposure time. additional i/o signals support the provision of an external mechanical shutter. pixel array the sensor core uses a bayer color pattern, as shown in figure 2. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. figure 2: pixel color pattern detail (top right corner) black pixels column readout direction . . . ... row readout direction gr b gr r gb r gr b gr r gb r first clear active pixel (110, 52) gr b gr
mt9j003-ds rev. e 5/15 en 8 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor operating modes operating modes by default, the mt9j003 powers up with th e serial pixel data in terface enabled. the sensor can operate in serial hispi or parallel mode. for low-noise operation, the mt9j003 requires separate power supplies for analog and digital power. incoming digital and analog ground conductors should be placed in such a way that coupling between the two are mini mized. both power supply rails should also be routed in such a way that noise coupli ng between the two supplies and ground is minimized. caution on semiconductor does not recommend the use of inductance filters on the power supplies or output signals. figure 3: typical configuration: serial four-lane hispi interface notes: 1. all power supplies shou ld be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the gpi pins can be statically pulled high or low to be used as module ids, or they can be pro- grammed to perform special functions (trigger, oe_n, s addr , standby) to be dynamically con- trolled. v dd _io v dd _slvs_tx v dd _pll v dd v aa v dd v dd _slvs v aa vaa_pix master clock (6C48 mhz) s data sclk reset_bar test extclk d gnd pixgnd a gnd digital ground analog ground gnd_pll digital core power 1 hispi phy i/o power 1 analog power 1 to controlle from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2, 3 analog power 1 vaa_pix slvsc_n slvsc_p slvs_0p slvs_0n slvs_1p slvs_1n slvs_2p slvs_2n slvs_3p slvs_3n flash shutter gpi[3:0] 4 v dd _slvs_tx
mt9j003-ds rev. e 5/15 en 9 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor operating modes 5. v pp , which can be used during the module manufactu ring process, is not shown in figure 3. this pad is left unconnected during normal operation. 6. the parallel interface output pads can be left un connected if the serial output interface is used. 7. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the mt9j00 3 demo headboard schematics for circuit recom- mendations 8. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 9. the signal path between the hispi serial transmitte r and receiver should be adequately designed to minimize any trans-impedance mismatch and/or reflections on the data path.
mt9j003-ds rev. e 5/15 en 10 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor operating modes figure 4: typical configuration: parallel pixel data interface notes: 1. all power supplies shou ld be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the gpi pins can be statically pulled high or low to be used as module ids, or they can be pro- grammed to perform special functions (trigger, oe_n, s addr , standby) to be dynamically con- trolled. 5. v pp , which can be used during the module manufactu ring process, is not shown in figure 4. this pad is left unconnected during normal operation. 6. the serial interface output pads can be left un connected if the parallel ou tput interface is used. 7. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the mt9j00 3 demo headboard schematics for circuit recom- mendations. 8. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 9. on semiconductor recommends that v dd _tx0 is tied to v dd when the sensor is using the parallel interface. vaa_pix v dd master clock (6C48 mhz) s data sclk reset_bar test flash frame_valid shutter d out [11:0] extclk d gnd pix gnd a gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk v dd _io gpi[3:0] 4 digital i/o power 1 1.5k 2 1.5k 2, 3 v dd _io v dd _pll v dd v aa v aa vaa_pix gnd_pll analog power 1 vdd_pll pll power 1 analog power 1 v dd _tx0
mt9j003-ds rev. e 5/15 en 11 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor signal descriptions signal descriptions table 1 provides signal descriptions for mt9j003 die. for pad location and aperture information, refer to the mt9j003 die data sheet. table 1: signal descriptions pad name pad type description extclk input master clock input, 6C48 mhz. reset_bar (xshutdown) input asynchronous active low reset. when asserted , data output stops and all internal registers are restored to their factory default settings. sclk input serial clock for access to control and status registers. gpi[3:0] input general purpose inputs. after reset, these pads ar e powered-down by default; this means that it is not necessary to bond to these pads. any of thes e pads can be configured to provide hardware control of the standby, output enable, s addr select, and shutter trigger functions. can be left floating if not used. test input enable manufacturing test modes. it should not be left floating. it can be tied to ground or v dd _io when used in parallel or hispi. it should be connected to d gnd for normal operation of the ccp2 configured sensor, or connected to v dd _io power for the mipi ? -configured sensor. s data i/o serial data from reads and writes to control and status registers. line_valid output line_valid (lv) output. qualified by pixclk. frame_valid output frame_valid (fv) output. qualified by pixclk. d out [11:0] output parallel pixel data output. qualified by pixclk. pixclk output pixel clock. used to qualify the lv, fv, and d out [11:0] outputs. flash output flash output. synchronization pulse for externa l light source. can be left floating if not used. shutter output control for external mechanical shutter. can be left floating if not used. v pp supply power supply used to program one-time programmable (otp) memory. disconnect pad when not programming or when feature is not used. v dd _tx0 supply phy power supply. digital power supply for th e mipi or ccp2 serial data interface. on semiconductor recommends that v dd _tx0 is always tied to v dd when using an unpackaged sensor. v dd _slvs supply hispi power supply for data and clock output. this should be tied to v dd v dd _slvs_tx supply digital power supply for the hispi i/o. v aa supply analog power supply. v aa _pix supply analog power supply for the pixel array. a gnd supply analog ground. v dd supply digital power supply. v dd _io supply i/o power supply. d gnd supply common ground for digital and i/o. v dd _pll supply pll power supply. gnd_pll supply pll ground. pixgnd supply pixel ground. slvs_0p output lane 1 differential hispi (lvds) serial data (positive). qualified by the slvs serial clock. slvs_0n output lane 1 differential hispi (lvds) serial data (negative). qualified by the slvs serial clock. slvs_1p output lane 2 differential hispi (lvds) serial data (positive). qualified by the slvs serial clock. slvs_1n output lane 2 differential hispi (lvds) serial data (negative). qualified by the slvs serial clock. slvs_2p output lane 3 differential hispi (lvds) serial data (positive). qualified by the slvs serial clock. slvs_2n output lane 3 differential hispi (lvds) serial data (negative). qualified by the slvs serial clock.
mt9j003-ds rev. e 5/15 en 12 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor signal descriptions figure 5: hispi package pinout diagram slvs_3p output lane 4 differential hispi (lvds) serial data (positive). qualified by the slvs serial clock. slvs_3n output lane 4 differential hispi (lvds) serial data (negative). qualified by the slvs serial clock. slvs_cp output differential hispi (lvds) serial clock (positive). qualified by the slvs serial clock. slvs_cn output differential hispi (lvds) serial clock (positive). qualified by the slvs serial clock. table 1: signal descriptions (continued) pad name pad type description 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 a gnd v aa nc vaa pixgnd vaa_pix vaa_pix nc nc v aa a gnd v dd _slvs v dd _io gnd v dd extclk v dd gnd v dd _io s data sclk test reset_bar v dd gnd v dd _io gpi0 gpi1 gpi2 gpi3 shutter flash gnd v dd _pll vpp v dd _slvs_tx slvs0_n slvs0_p slvs1_n slvs1_p slvsc_n slvsc_p slvs2_n slvs2_p slvs3_n slvs3_p gnd nc
mt9j003-ds rev. e 5/15 en 13 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor signal descriptions figure 6: 48-pin ilcc parallel package pinout diagram 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 nc pixgnd v aa a gnd vaa_pix vaa_pix v aa a gnd v aa v pp nc nc d out 7 d out 8 d out 9 d out 10 d out 11 v dd_ io pixclk v dd sclk s data reset_bar v dd _io v dd gpi0 gpi1 gpi2 gpi3 gnd test flash shutter frame_valid line_valid gnd gnd extclk v dd _pll d out 0 d out 1 d out 2 d out 3 d out 4 d out 5 d out 6 gnd nc
mt9j003-ds rev. e 5/15 en 14 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format output data format serial pixel data interface the mt9j003 supports raw8, raw10, and raw12 image data formats over a serial inter- face. the sensor supports a 1 and 2-lane mipi as well as the hispi interface. these inter- faces are not described in the data sheet. high speed serial pixel interface the high speed serial pixel (hispi) interface uses four data and one clock low voltage differential signaling (lvds) outputs. ? slvs_cp, slvs_cn ? slvs_[0:3]p, slvs_[0:3]n the hispi interface supports two protocols, streaming and packetized. the streaming protocol conforms to a standard video a pplication where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. the pack- etized protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 7 shows the configuration between the hispi transmitter and the receiver. figure 7: hispi transmitter and receiver interface block diagram a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0
mt9j003-ds rev. e 5/15 en 15 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format hispi physical layer the hispi physical layer is partitioned into bl ocks of four data lanes and an associated clock lane. any reference to the phy in the remainder of this document is referring to this minimum building block. the phy will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the following edge of clock. figure 8 shows bit transmission. in this example, the wo rd is transmitted in order of msb to lsb. the receiver latches data at the ri sing and falling edge of the clock. figure 8: timing diagram dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. figure 9: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay del0[2:0] delay del1[2:0] delay delay del3[2:0] delay del2[2:0] data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 delclock[2:0]
mt9j003-ds rev. e 5/15 en 16 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format figure 10: delaying the clock_lane with respect to data_lane figure 11: delaying data_lane with respect to the clock_lane hispi streaming mode protocol layer the protocol layer is position ed between the output data path of the sensor and the physical layer. the main functions of the protocol layer are generating sync codes, formatting pixel data, inserting horizontal/v ertical blanking codes, and distributing pixel data over defined data lanes. the hispi interface can only be configured when the sensor is in standby. this includes configuring the interface to transmit across 1, 2, or all 4 data lanes. datan (de ln = 000) cp ( delclock = 000) cp (delclock = 001) cp (delclock = 010) cp (de lclock = 011) cp ( delclock = 100) cp (d elcloc k = 1 01) c p (delclock = 110) cp ( delclock =111) increasing delclock_[2:0] increases clock delay 1 ui 1 ui t dllstep cp ( delclock = 000) datan (deln = 000) datan(deln = 001) datandeln = 010) datan(deln = 011) datan(deln = 100) datan(deln = 101) datan(deln = 110) datan(deln = 111) increasing deln_[2:0] increases data delay
mt9j003-ds rev. e 5/15 en 17 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format protocol fundamentals referring to figure 12, it can be seen that a sync code is inserted in the serial data stream prior to each line of image data. the streaming protocol will insert a sync code to transmit each active data li ne and vertical blanking lines. the packetized protocol will tr ansmit a sync code to note the start and end of each row. the packetized protocol uses sync a ?start of frame? (sof) sync code at the start of a frame and a ?start of line? (sol) sync code at the start of a line within the frame. the protocol will also transmit an ?end of frame? (eof) at the end of a frame and an ?end of line? (eol) sync code at the end of a row within the frame figure 12: steaming vs. packetized transmission parallel pixel data interface mt9j003 image data is read out in a progress ive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 13. the amount of hori- zontal blanking and vertical blanking is pr ogrammable; lv is high during the shaded region of the figure. fv timing is described in the ?output data timing (parallel pixel data interface)?. ?
mt9j003-ds rev. e 5/15 en 18 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format figure 13: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 valid image horizontal blanking 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 vertical blanking vertical/horizontal blanking
mt9j003-ds rev. e 5/15 en 19 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format output data timing (paralle l pixel data interface) mt9j003 output data is synchronized with the pixclk output. when lv is high, one pixel value is output on the 12-bit d out output every pixclk period. the pixel clock frequency can be determined based on the sensor's master input clock and internal pll configuration. the rising edges on the pixclk signal occurs one-half of a pixel clock period after transitions on lv, fv, and d out (see figure 14). this allows pixclk to be used as a clock to sample the data. pixclk is continuously enabled, even during the blanking period. the mt9j003 can be programmed to delay the pixclk edge relative to the d out transitions. this can be achieved by programming the corresponding bits in the row_speed register. the parameters p, a, and q in figure 15 are defined in table 2 on page 19. figure 14: pixel data timing example figure 15: row timing and fv/lv signals the sensor timing (shown in table 2 on pa ge 19) is shown in terms of pixel clock and master clock cycles (see figure 14 on page 19). the default settings for the on-chip pll generate a pixel array clock (vt_pix_clk) of 160 mhz an d an output clock (op_pix_clk) of 40 mhz given a 20 mhz input clock to the mt9j003. eq uations for calculating the frame rate are given in ?frame rate control? on page 47. table 2: row timing with hispi interface parameter name equation default timing pixclk_period pixel clock period 1/vt_pix_clk_freq_mhz 1 pixel clock = 6.25ns p 0 [11:0] p 1 [11:0] p 2 [11:0] p 3 [11:0] p 4 [11:0] p 5 p n-2 p n-1 [11:0] p n [11:0] valid image data blanking blanking lv pixclk d out [11:0] fv lv number of master clocks p a q aqap
mt9j003-ds rev. e 5/15 en 20 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format s skip (subsampling) factor for x_odd_inc = y_odd_inc = 3, s = 2. for x_odd_inc = y_odd_inc = 7, s = 4. otherwise, s = 1 for y_odd_inc = 3, s = 2 for y_odd_inc = 7, s = 4 for y_odd_inc = 15, s = 8 for y_odd_inc = 31, s = 16 for y_odd_inc = 63, s = 32 1 a active data time (x_addr_end C x_addr_start + x_odd_inc)*0.5 *pixclk_period/s = 3775 - 112 + 12 1832 pixel clocks = 11.45 ? s p frame start/end blanking 6 * pixclk_period 6 pixel clocks = 37.5ns q horizontal blanking (line_length_pck C a) * pixclk_period = 3694 C 1832 1862 pixel clocks = 11.63 ? s a + q row time line_length_pck * pixclk_period 3694 pixel clocks = 23.09 ? s n number of rows (y_addr_end - y_addr_start + y_odd_inc) / s = (2755 - 8 + 1)/1 2748 rows vvertical blanking ((frame_length_lines - n) * (a + q)) + q C (2 * p) = (2891 - 2748) *3694 + 1862 - 12 530092 pixel clocks = 3.31ms t frame valid time (n * (a + q)) - q + (2 * p) = 2748*3694 - 1862 + 12 10149262 pixel clocks = 63.42ms f total frame time line_length_pck * frame_leng th_lines * pixclk_period = 2891 *3694 10679354 pixel clocks = 66.75ms table 3: row timing with parallel interface parameter name equation default timing pixclk_period pixel clock pe riod 1/vt_pix_clk_freq_mhz 1 pixel clock = 6.25ns s skip (subsampling) factor for x_odd_inc = y_odd_inc = 3, s = 2. for x_odd_inc = y_odd_inc = 7, s = 4. otherwise, s = 1 for y_odd_inc = 3, s = 2 for y_odd_inc = 7, s = 4 for y_odd_inc = 15, s = 8 for y_odd_inc = 31, s = 16 for y_odd_inc = 63, s = 32 1 aactive data time (x_addr_end - x_addr_start + x_odd_inc)*0.5*pixclk_period/s = (3775-112+1)/2 1832 pixel clocks = 11.45 ? s p frame start/end blanking 6 * pixclk_period 6 pixel clocks = 75ns q array horizontal blanking (line_length_pck C a) * pixclk_period = 7358 C 1832 5526 pixel clocks = 34.5 ? s external horizontal blanking is 30 pixel clocks or 187ns. a + q row time limited by output interface speed x_output_size*clk_pixel/clk_op + 30 = 3664*160mhz/80mhz + 30 7358 pixel clocks = 46.1 ? s n number of rows (y_addr_end - y_addr_start + y_odd_inc) / s = (2755 - 8 + 1)/1 2748 rows table 2: row timing with hispi interface (continued) parameter name equation default timing
mt9j003-ds rev. e 5/15 en 21 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format v vertical blanking ((frame_length_lines - n) * (a + q)) + q C (2 * p) = (2891 - 2748)*7358 + 1862 - 12 1054044 pixel clocks = 6.59ms t frame valid time (n * (a + q)) - q + (2 * p) = 2748*7358 - 1862 + 12 20217934 pixel clocks = 126.36ms ftotal frame time line_length_pck * frame_length_lines * pixclk_period = 2891*37358 21271978pixel clocks = 132.95ms table 4: row timing with parallel interface using low power mode parameter name equation default timing pixclk_period pixel clock pe riod 1/vt_pix_clk_freq_mhz 1 pixel clock = 12.5ns s skip (subsampling) factor for x_odd_inc = y_odd_inc = 3, s = 2. for x_odd_inc = y_odd_inc = 7, s = 4. otherwise, s = 1 for y_odd_inc = 3, s = 2 for y_odd_inc = 7, s = 4 for y_odd_inc = 15, s = 8 for y_odd_inc = 31, s = 16 for y_odd_inc = 63, s = 32 1 aactive data time (x_addr_end - x_addr_start + x_odd_inc)*0.5*pixclk_period/s = (3775-112+1)/2 1832 pixel clocks = 22.9 ? s p frame start/end blanking 6 * pixclk_period 6 pixel clocks = 75ns q array horizontal blanking (line_length_pck C a) * pixclk_period = 3694 C 1832 1862 pixel clocks = 23.2 ? s external horizontal blanking is 30 pixel clocks or 375ns. a + q row time limited by output interface speed x_output_size*clk_pixel/clk_op + 30 = 3664*80mhz/80mhz + 30 3694 pixel clocks = 46.1 ? s n number of rows (y_addr_end - y_addr_start + y_odd_inc) / s = (2755 - 8 + 1)/1 2748 rows v vertical blanking= ((frame_length_lines - n) * (a + q)) + q C (2 * p) = (2891 - 2748)*7358 + 1862 - 12 530092 pixel clocks = 6.63ms t frame valid time (n * (a + q)) - q + (2 * p) = 2748*3694 - 1862 + 12 10149262 pixel clocks = 126.86ms ftotal frame time line_length_pck * frame_length_lines * pixclk_period = 2891*3694 10679354 pixel clocks = 133.5ms table 3: row timing with parallel interface (continued) parameter name equation default timing
mt9j003-ds rev. e 5/15 en 22 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor output data format frame rates at common resolutions table 5 shows examples of register settings to achieve common resolutions and their frame rates. table 5: register settings for common resolutions resolution interface frame rate subsampling mode x_addr_start x_addr_end y_addr_start y_addr_end 3664x2748 (full resolution) hispi 14.7 fps n/a 112 3775 8 2755 parallel 7.5 fps 1920x1080 (1080p hdtv) hispi 59.94 fps 2x2 summing 32 3873 296 2453 parallel 29.97 fps 1280x720 (720p hdtv) hispi and parallel 59.94 fps 2x2 summing 32 3873 296 2453 1408x792 + 10% eis (720p hdtv + 10% eis) hispi and parallel 59.94 fps 2x2 summing 624 3437 304 1885 640x480 (low power monitor) hispi and parallel 29.97 fps sum2skip2 112 3769 8 2753
mt9j003-ds rev. e 5/15 en 23 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the mt9j003. the interface protoc ol uses a master/slave model in which a master controls one or more slave devices. th e sensor acts as a slave device. the master generates a clock (sclk) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol dete rmines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive sclklow; the mt9j003 uses sclk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while sclk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while sclk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the mt9j003 for the mipi configured sensor are 0x6c (write address) and 0x6d (read address) in a ccordance with the mipi specification. alter- nate slave addresses of 0x6e(write address) and 0x6f(read address) can be selected by enabling and asserting the s addr signal through the gpi pad. but for the ccp2 config- ured sensor, the default slave addresses used are 0x20 (write address) and 0x21 (read
mt9j003-ds rev. e 5/15 en 24 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor two-wire serial register interface address) in accordance with the smia specif ication. also, alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr signal through the gpi pad. an alternate slave address can al so be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when sclk is low and must be stable while sclk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
mt9j003-ds rev. e 5/15 en 25 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 16) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 16 shows how the internal register address maintained by the mt9j003 is loaded and incremented as the sequence proceeds. figure 16: single read from random location single read from current location this sequence (figure 17) performs a read using the current value of the mt9j003 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 17: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a
mt9j003-ds rev. e 5/15 en 26 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 18) starts in the same way as the single read from random loca- tion (figure 16). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 18: sequential read, start from random location sequential read, start from current location this sequence (figure 19) starts in the same way as the single read from current loca- tion (figure 17 on page 25). instead of gener ating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 19: sequential read, start from current location single write to random location this sequence (figure 20) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 20: single write to random location slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+1 a a write data
mt9j003-ds rev. e 5/15 en 27 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 21) starts in the same way as the single write to random location (figure 20 on page 26). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master gene rates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 21: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
mt9j003-ds rev. e 5/15 en 28 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor programming restrictions programming restrictions the following sections list programming rules that must be adhered to for correct opera- tion of the mt9j003. x address restrictions the minimum column address available for the sensor is 24. the maximum value is 3879. effect of scaler on legal range of output sizes when the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size genera ted by the scaler. the mt9j003 will operate incorrectly if the x_output_size and y_outpu t_size are significantly larger than the output image. to understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). this situation is shown in figure 1. figure 1: effect of limiter on the data path in figure 1, three different stages in the data path (see ?timing specifications? on page 61) are shown. the first stage is the output of the sensor core. the core is running at full resolution and x_output_size is set to ma tch the active array si ze. the lv signal is asserted once per row and remains asserted for n pixel times. the pixel_valid signal toggles with the same timing as lv, indicating that all pixels in the row are valid. the second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. the effe ct of the scaler is to combine groups of pixels. therefore, the row time remains the same, but only half the pixels out of the scaler are valid. this is signaled by transi tions in pixel_valid. overall, pixel_valid is asserted for ( n /2) pixel times per row. table 1: definitions for programming rules name definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3; xskip = 4 if x_odd_inc = 7 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3; yskip = 4 if y_odd_inc = 7; yskip = 8 if y_odd_inc = 15; yskip = 16 if y_odd_inc = 31; yskip = 32 if y_odd_inc = 63 core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 line_valid pixel_valid pixel_valid
mt9j003-ds rev. e 5/15 en 29 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor programming restrictions the third stage is the output of the limiter when the x_output_size is still set to match the active array size. because the scaler has reduced the amount of valid pixel data without reducing the row time, the limiter attempts to pad the row with ( n /2) additional pixels. if this has the effect of extending lv across th e whole of the horizontal blanking time, the mt9j003 will cease to generate output frames. a correct configuration is shown in figure 2, in addition to showing the x_output_size reduced to match the output size of the scaler . in this configuration, the output of the limiter does not extend lv. figure 2 also shows the effect of the output fifo, which forms the final stage in the data path. the output fifo merges the intermittent pixel data back into a contiguous stream. although not shown in this example, the outp ut fifo is also capable of operating with an output clock that is at a diffe rent frequency from its input clock. figure 2: timing of data path core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 pixel_valid line_valid pixel_valid output fifo: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 line_valid pixel_valid
mt9j003-ds rev. e 5/15 en 30 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor programming restrictions output data timing the output fifo acts as a boundary between two clock domains. data is written to the fifo in the vt (video timing) clock domain. data is read out of the fifo in the op (output) clock domain. when the scaler is disabled, the data rate in the vt clock domain is constant and uniform during the active period of each pi xel array row readout. when the scaler is enabled, the data rate in the vt clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. a key constraint when configuring the clock fo r the output fifo is that the frame rate out of the fifo must exactly match the frame rate into the fifo. when the scaler is disabled, this constraint can be met by imposi ng the rule that the row time on the serial data stream must be greater than or equal to the row time at the pixel array. the row time on the serial data stream is calculated from the x_output_size and the data_format (8, 10, or 12 bits per pixel), and must include the time taken in the serial data stream for start of frame/row, end of row/frame and checksum symbols. caution if this constraint is not met, the fifo will either underrun or overrun. fifo underrun or over- run is a fatal error condition that is signalled through the data path_status register (r0x306a). changing registers while streaming the following registers should only be repr ogrammed while the sensor is in software standby: ?vt_pix_clk_div ? vt_sys_clk_div ? pre_pll_clk_div ? pll_multiplier ? op_pix_clk_div ?op_sys_clk_div programming restrictions when using global reset interactions between the registers that co ntrol the global reset imposes some program- ming restrictions on the way in which they are used; these are discussed in "global reset" on page 52.
mt9j003-ds rev. e 5/15 en 31 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface control of the signal interface this section describes the operation of the signal interface in all functional modes. serial register interface the serial register interface uses these signals: ?sclk ?s data ?s addr (through the gpi pad) sclk is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place th is signal in high-z, an external pull-up resistor should be connected on this signal. s data is a bidirectional signal. an external pull-up resistor should be connected on this signal. s addr is a signal, which can be optionally enable d and controlled by a gpi pad, to select an alternate slave address. these slave addresses can also be programmed through r0x31fc. this interface is described in detail in "two-wire serial register interface" on page 23. parallel pixel data interface the parallel pixel data interfac e uses these output-only signals: ?fv ?lv ?pixclk ?d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. table 3 on page 32 shows the recommended settings. when the parallel pixel data interface is in us e, the serial data output signals can be left unconnected. set reset_register[12] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is en abled, its signals can be switched asynchro- nously between the driven and high-z under pin or register control, as shown in table 2. selection of a pin to use for the oe_n functi on is described in "general purpose inputs" on page 35. table 2: output enable control oe_n pin drive signals r0x301aCb[6] description disabled 0 interface high-z disabled 1 interface driven 1 0 interface high-z x1interfacedriven 0xinterfacedriven
mt9j003-ds rev. e 5/15 en 32 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 3. table 3: configuration of the pixel data interface serializer disable r0x301 aCb[12] parallel enable r0x301aCb[7] standby end-of-frame r0x301aCb[4] description 0 0 1 power up default. serial pixel data interface and its clocks are enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.
mt9j003-ds rev. e 5/15 en 33 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface system states the system states of the mt9j003 are repr esented as a state diagram in figure 3 and described in subsequent sections. the effect of reset_bar on the system state and the configuration of the pll in the different states are shown in table 4 on page 34. the sensor?s operation is broken down into three separate states: hardware standby, software standby, and streaming. the tran sition between these states might take a certain amount of clock cyc les as outlined in table 4. figure 3: mt9j003 system states powered off streaming powered on por =1 reset _bar transitions 1 -> 0 (asynchronous from any state ) initialization timeout two-wire serial interface write mode_select = 0 pll lock pll locked software reset initiated (synchronous from any state) wait for frame end software standby two-wire serial interface write mode_select = 1 two-wire serial interface write software_reset = 1 internal initialization hardware standby 2400 extclk cycles reset_bar = 0 por = 0 reset_bar = 1 pll not locked por active (only if por is on sensor) power supplies turned off (asychronous from any state) frame in progress
mt9j003-ds rev. e 5/15 en 34 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface note: vco = voltage-controlled oscillator. power-on reset sequence when power is applied to the mt9j003, it en ters a low-power hardware standby state. exit from this state is controlled by the later of two events: 1. the negation of the reset_bar input. 2. a timeout of the internal power-on reset circuit. it is possible to hold reset_bar permanently de-asserted and rely upon the internal power-on reset circuit. when reset_bar is asserted it asynchronous ly resets the sensor, truncating any frame that is in progress. when the sensor leaves the hardware standby st ate it performs an in ternal initialization sequence that takes 2400 extclk cycles. af ter this, it enters a low-power software standby state. while the initialization sequence is in progress, the mt9j003 will not respond to read transactions on its two-wire serial interface. therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, r0x0000. while the initialization sequ ence is in progress, the sensor will not respond to its device address and reads from the sensor will result in a nack on the two-wire serial interface bus. when the sequ ence has completed, reads will return the operational value for the register (0x2800 if r0x0000 is read). when the sensor leaves software standby mo de and enables the vco, an internal delay will keep the pll disconnected for up to 1ms so that the pll can lock. the vco lock time is 200s(typical) , 1ms (maximum). soft reset sequence the mt9j003 can be reset under software co ntrol by writing ?1? to software_reset (r0x0103). a software reset asynchronously re sets the sensor, truncating any frame that is in progress. the sensor starts the intern al initialization sequence, while the pll and analog blocks are turned off. at this point, the behavior is exactly the same as for the power-on reset sequence. signal state during reset table 5 on page 35 shows the state of the signal interface during hardware standby (reset_bar asserted) and the default state du ring software standby. after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values. table 4: reset_bar and pll in system states state extclks pll powered off x vco powered down por active x hardware standby 0 internal initialization 1 software standby pll lock vco powering up and locking, pll output bypassed streaming vco running, pll output active wait for frame end
mt9j003-ds rev. e 5/15 en 35 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface general purpose inputs the mt9j003 provides four general purpose in puts. after reset, the input pads associ- ated with these signals are powered down by de fault, allowing the pads to be left discon- nected/floating. the general purpose inputs are enabled by setting reset_register[8] (r0x301a). once enabled, all four inputs must be driven to valid logic levels by external signals. the state of the general purpose inputs can be read through gpi_status[3:0] (r0x3026). in addition, each of the following functions ca n be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input: ? output enable (see ?output enable control? on page 31) ? trigger (see the sections below) ? standby functions ?s addr selection (see ?serial register interface? on page 31) the gpi_status register is used to associ ate a function with a general purpose input. table 5: signal state during reset pad name pad type hardware standby software standby extclk input enabled. must be driven to a valid logic level. reset_bar (xshutdown) gpi[3:0] powered down. can be left disconnected/floating. test enabled. must be driven to a logi c 0 for a serial ccp2-configured sensor, or 1 for a serial mipi-configured sensor. sclk enabled. must be pulled up or driven to a valid logic level. s data i/o enabled as an input. must be pulled up or driven to a valid logic level. line_valid output high-z. can be left disconnected or floating. frame_valid d out [11:0] pixclk slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n clk_p clk_n flash high-z. logic 0. shutter
mt9j003-ds rev. e 5/15 en 36 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface streaming/standby control the mt9j003 can be switched between its so ft standby and streaming states under pin or register control, as shown in table 6. se lection of a pin to use for the standby func- tion is described in ?general purpose inputs? on page 35. the state diagram for transi- tions between soft standby and streaming states is shown in figure 3 on page 33. trigger control when the global reset feature is in use, the trigger for the sequence can be initiated either under pin or register control, as show n in table 7. selection of a pin to use for the trigger function is described in ?general purpose inputs? on page 35. table 6: streaming/standby standby streaming r0x301aCb[2] description disabled 0 soft standby disabled 1 streaming x0 soft standby 0 1 streaming 1x soft standby table 7: trigger control trigger global trigger r0x3160C1[0] description disabled 0 idle disabled 1 trigger 00 idle x 1 trigger 1 x trigger
mt9j003-ds rev. e 5/15 en 37 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface pll the sensor contains a pll for timing generation and contro l. the pll contains a pres- caler to divide the input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks . the clocking structure is shown in figure 4. figure 4: clocking structure figure 4 shows the different clocks and the register names. it also shows the default setting for each divider/multiplier control regi ster, and the range of legal values for each divider/multiplier control register. the vt and op sys clk divider is hardwired in the design. the pll default setting s support the hispi interface. from the diagram, the clock frequencies can be calculated for the hispi interface using a 15 mhz input clock as follows: internal pixel clock used to readout the pixel array: (eq 1) external pixel clock used to output the data: (eq 2) internal master clock: (eq 3) the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock. ? the divisors that are used to control each clock. pre _ pll _ clk _ div ( n ) 2 ( 1 - 64 ) pll _ multiplier (m ) 64 ( 32 - 128 ) extclk pre pll divider pll multiplier (m) op sys clk divider clk _ pixel divider e x t e r n a l i n p u t c l o c k e x t _ c l k _ f r e q _ m h z op pix clk divider op _ pix _clk _div 1 2 ( 8 , 1 0 , 1 2 ) row _ speed [ 2 : 0 ] 1 ( 1 , 2 , 4 ) pll output clock vt sys clk divider 1 ( 1 , 2 , 4 , 6 , 8 ) vt pix clk divider clk _ op divider 3 ( 2 , 3 , 4 , 5 , 6 , 7 , 8 ) row _ speed [10 :8 ] 1 ( 1 , 2 , 4 ) p l l i n p u t c l o c k p l l _ i p _ c l k _ f r e q p l l i n t e r n a l v c o f r e q u e n c y v t _ p i x _ c l k _ d i v c l k _ p i x e l v t _ p i x _ c l k v t _ s y s _ c l k o p _ s y s _ c l k o p _ p i x _ c l k c l k _ o p 1 ( 1 , 2 , 4 , 6 , 8 ) clk_pixel_freq_mhz = ext_clk_freq_mhz x pll_multiplier pre_pll_clk_div x vt_pix_clk_div x row_speed [2:0] ----------------------------------------------------------------------------------------------------------------------------- - = 15 mhz x 64 2x 3 x1 --------------------------------- = 160 mhz clk_op_freq_mhz = ext_clk_freq_mhz x pll_multiplier pre_pll_clk_div x op_pix_clk _div x row_speed [10:8] ------------------------------------------------------------------------------------------------------------------------------- --- = 15 mhz x 64 2x 12 x1 --------------------------------- = 40 mhz vt_pix_clk_freq_mhz/2
mt9j003-ds rev. e 5/15 en 38 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor control of the signal interface the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met. ? pll_ip_clk_freq must be in the range 6? 48 mhz. higher frequencies are preferred. ?pll internal vco frequency must be in the range 384?768 mhz. the minimum/maximum value for the divider/multiplier must be met. ? range for m: 32?128. ? range for (n): 1?64. ? the op_pix_clk must never run faster than the vt_pix_clk to ensure that the output data stream is contiguous. when using the hispi serial interface, the op_pix_clk must be 1/ 4 of the vt_pix_clk. ? the op_pix_clk_div divider must match the bit-depth of the image when using hispi. for example, op_pix_clk_div must be set to 12 for a 12-bit hispi output. the is not required when using the parallel interface. ? when using the parallel interface, the op_p ix_clk must be half of the vt_pix_clk. ? the output line time (including the nece ssary blanking) must be output in a time equal to or less than the time defined by line_length_pck. although the pll vco input frequency range is advertised as 6?48 mhz, superior performance is obtained by keeping the vco input frequency as high as possible. the usage of the output clocks is shown below: ? clk_pixel is used by the sensor core to control the timing of the pixel array. the sensor core produces one 12-bit pixel each vt_pix_clk period. the line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the clk_pixel period. ? clk_op is used to load parallel pixel data from the output fifo. the output fifo generates one pixel each op_pix_clk period. an example of the parallel configuration for th e pll will uses an input clock of 10 mhz, an internal pixel clock of 160 mhz, and an ou tput clock of 80 mhz. in this configuration: n = 1 m = 64 vt_sys_clk_div = 2 op_sys_clk_div = 1 vt_pix_clk_div = 2 op_pix_clk_div = 8 internal pixel clock used to readout the pixel array: (eq 4) the external pixel clock us ed to output the data: programming the pll divisors the pll divisors must be programmed while the mt9j003 is in the software standby state. after programming the divisors, wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. clk_pixel_freq_mhz = ext_clk_freq_mhz x pll_multiplier pre_pll_clk_div x vt_pix_clk_div x row_speed [2:0] ----------------------------------------------------------------------------------------------------------------------------- - = 10 mhz x 64 122 ? ? --------------------------------- = 160 mhz clk_op_freq_mhz = ext_clk_freq_mhz x pll_multiplier pre_pll_clk_div x op_pix_clk _div x row_speed [10:8] ------------------------------------------------------------------------------------------------------------------------------- --- = 10 mhz x 64 1 x 1 x 8 --------------------------------- = 80 mhz
mt9j003-ds rev. e 5/15 en 39 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor features an external timer will need to delay the entr ance of the streaming mode by 1 millisecond so that the pll can lock. the effect of programming the pll divisors while the mt9j003 is in the streaming state is undefined. clock control the mt9j003 uses an aggressive clock-gating methodology to reduce power consump- tion. the clocked logic is divided into a number of separate domains, each of which is only clocked when required. when the mt9j003 enters a low-power state, almost all of the internal clocks are stopped. the only exception is that a smal l amount of logic is clocked so that the two-wire serial interface continues to respond to read and write requests. features scaler the mt9j003 sensor includes scaling capabilities. this allows the user to generate full field-of-view, low resolution images. scaling is advantageous because it uses all pixel values to calculate the output image which help s to avoid aliasing. it is also more conve- nient than binning because the scale factor va ries smoothly and the user is not limited to certain ratios of size resolution. the scaling factor is programmable in 1/16 steps. (eq 5) scale_n is fixed at 16. scale_m is adjustable with r0x0404 legal values for m are 16 through 128. the user has the ability to scale from 1:1 ( m = 16) to 1:8 ( m = 128). shading correction lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing color plane nonuniformity in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9j003 has an embedded shading correction module that can be programmed to counter the shading effects on each individual red, greenb, greenr, and blue color signal. the correction function color-dependent solutions are calibrated using the sensor, lens system and an image of an evenly illuminated, featureless gray ca libration field. from the resulting image, register values for the color correction function (coefficients) can be derived. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 6) scalefactor = scale_n scale_m -------------------- - = 16 scale_m ------------ -------- - pcorrected row, col ?? = psensor(row,col) * f(row,col)
mt9j003-ds rev. e 5/15 en 40 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor features where p are the pixel values and f is the color dependent correction functions for each color channel. each function includes a set of color-dependent coefficients defined by registers r0x3600?3726. the function's origin is the cent er point of the function used in the calcu- lation of the coefficients. using an origin near the central point of symmetry of the sensor response provides the best results. th e center point of the function is determined by origin_c (r0x3782) and origin_r (r0x3784) and can be used to counter an offset in the system lens from the center of the sensor array. one-time programmable memory the mt9j003 has a two-byte otp memory that can be utilized during module manufac- turing to store specific information about the module. this feature provides system inte- grators and module manufacturers the abilit y to label and distinguish various module types based on lens, ir-cut filter, or other properties. during the programming process, a dedicated pin for high voltage needs to be provided to perform the anti-fusing operation. this voltage (v pp ) would need to be 8.5v + 3%. instantaneous v pp cannot exceed 9v at any time. the completion of the programming process will be communicated by a register through the two-wire serial interface. because this programming pin needs to sustain a higher voltage than other input/ output pins, having a dedicated high voltage pin (v pp ) minimizes the design risk. if the module manufacturing process can probe the sensor at the die or pcb level (that is, supply all the power rails, clocks, two-wire se rial interface signals), then this dedicated high voltage pin does not need to be assigned to the module connector pinout. however, if the v pp pin needs to be bonded out as a pin on the module, the trace for v pp needs to carry a maximum of 1ma is needed for programming only. this pin should be left floating once the module is integrated to a design. if the v pp pin does not need to be bonded-out as a pin on the module, it should be left floating inside the module. the programming of the otp memory requires the sensor to be fully powered and remain in software standby with its clock input applied. the information will be programmed through the use of the two-wire serial interface, and once the data is written to an internal register, the programming host machine will apply a high voltage to the programming pin, an d send a program command to initiate the anti-fusing process. after the sensor has finished programming the otp memory, a status bit will be set to indicate the end of the programming cycle, and the host machine can poll the setting of the status bit through the two-wi re serial interface. only one programming cycle for the 16-bit word can be performed. reading the otp memory data requires the se nsor to be fully powered and operational with its clock input applied. the data can be read through a register from the two-wire serial interface. the steps below describe the process to program and verify the programmed data in the otp memory: 1. apply power to all the power rails of the sensor (v dd , v dd _io, v aa , v aa _pix, v dd _pll, and vdd_tx0). 1a. set v aa to 3.1v during otp memory programming phase. 1b. v pp needs to be floated during this phase. 1c. other supplies at nominal. 2. provide 24 mhz extclk clock input. the pll settings are discussed at the end of the document.
mt9j003-ds rev. e 5/15 en 41 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor features 3. perform the proper reset sequence to the sensor. 4. place the sensor in soft standby (sensor default state upon power-up) or ensure the streaming is turned off when the part is in active mode. 5. v pp ramps to 8.5v in preparation to program. power supply (v pp ) slew rate should be slower than 1v/s. 6. program r0x3052 to the value 0x045c. 7. program r0x3054 to the value 0xea99. 8. write the 16 bit word data by programming r0x304c. 9. initiate the otp memory programming pr ocess by programming r0x304a[0] to the value 0x0001. 10. check r0x304a [2] = 1, until bit is set to ?1? to check for program completion. 11. repeat steps 9 and 10 two more times. 12. remove high voltage and float v pp pin. 13. power down the sensor. 14. apply nominal power to all the power rails of the sensor v dd , v dd _io, v aa , v aa _pix and v dd _pll). v pp must be floated. 15. set extclk to normal or cust omer defined operating frequency. 16. perform the proper reset sequence to the sensor. 17. initiate the otp memory reading process by setting r0x304a[4] to the value 0x0010. 18. poll the register bit r0x304a[6] until bit set to ?1? to check for read completion. 19. read the 16 bit word data from the r0x304e. figure 5: sequence for programming the mt9j003 power supplies reset_bar extclk sclk/sdata v pp information to be initiate programming read programmed programmed to the register. and poll status bit. values for status.
mt9j003-ds rev. e 5/15 en 42 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration sensor readout configuration image acquisition modes the mt9j003 supports two image acquisition modes: 1. electronic rolling shutter (ers) mode this is the normal mode of operation. wh en the mt9j003 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic wi thin the sensor sequen ces through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. when the integration time is changed (by using the two- wire serial interface to change register settings), the timing and control logic contro ls the transition from old to new integra- tion time in such a way that the stream of output frames from the mt9j003 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the mt9j003 register ref- erence. 2. global reset mode this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration ti me is controlled by an external electro- mechanical shutter, and the mt9j003 provid es control signals to interface to that shutter. the operation of this mode is described in detail in "global reset" on page 52. the benefit of using an external electromechani cal shutter is that it eliminates the visual artifacts associated with ers operation. visu al artifacts arise in ers operation, particu- larly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is contro lled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. for both parallel and serial interfaces, the output image size is controlled by the x_ou tput_size and y_output_size registers. pixel border the default settings of the sensor provide a 3840h x 2748v image. a border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_ou tput_size, and y_output_size registers accordingly. this provides a total active pixel array of 3856h x 2764v including border pixels.
mt9j003-ds rev. e 5/15 en 43 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration readout modes horizontal mirror when the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. figure 6 shows a sequence of 6 pixels being read out with horizon- tal_mirror = 0 and horizontal_mirror = 1. changing horizontal_mirror causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 6: effect of horizontal mirror on readout order vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 7 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. changing vertical_flip ca uses the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 7: effect of vertical flip on readout order g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] g0[11:0] line_valid horizontal_mirror = 0 d out [11:0] horizontal_mirror = 1 d out [11:0] row0[11:0] row1[11:0] row2[11:0] row3[11:0] row4[11:0] row5[11:0] row5[11:0] row4[11:0] row3[11:0] row2[11:0] row0[11:0] frame_valid vertical_flip = 0 d out [11:0] vertical_flip = 1 d out [11:0] row1[11:0]
mt9j003-ds rev. e 5/15 en 44 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration subsampling the mt9j003 supports subsampling. this featur e allows the sensor to read out a sample of pixels available on the array. the most common subsampling used is either a 2x2 or 4x4 where every 2nd or 4th pixel is read in the x and y direction. figure 8: pixel array readout with out subsampling and with 2x2 skipping pixel skipping can be co nfigured up to 4x in the x-direction and 32x in the y-direction. skipping pixels in the x-direction will reduce the row-time while skipping in the y-direc- tion will reduce the number of rows readout from the sensor. skipping in both directions will reduce the frame-time and is a common method used to increase the sensor frame- rate. skipping will introduce image artifacts from aliasing. figure 9: combinations of pixel skipping in the mt9j003 sensor full resolution 2 x 2 skipping skip 2x skip 4x skip 32x, 16x, or 8x
mt9j003-ds rev. e 5/15 en 45 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration the subsampling feature can also bin or sum the skipped pixels. pixel binning will sample pixels and average the value together in the analog domain. summing will add the charge or voltage values of the neighboring pixels together. figure 10: pixel binning and summing the pixel summing must be done with adjacent pixels within the same color plane. the pixel binning can be configured to combine adjacent pixels or to combine every other pixel. the pixel subsampling can be configured as a combination of skipping and binning or summing. this type of subsampling is typically used to achieve the best combination of pixel responsivity and frame rate. the summi ng and skipping impl ementation will sum neighboring pixels on the same color plane and skip over the adjacent group of pixels. figure 11 on page 46 shows that neighborin g pixels are summed together. in the case that a subsampling factor of 4x or greater is used with summing, the neighboring pixels will also be summed together. 2x2 binning or summing v v e - e - summing avg avg avg avg binning
mt9j003-ds rev. e 5/15 en 46 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration figure 11: pixel skipping combined with summing or binning table 8 shows the different combinations of subsampling available with the mt9j003 sensor. the sensor cannot combine pixels using two different methods in the same direction. this means that bin-xy and sum-y are not valid combinations with the sensor. as well, the bin-xy is limited to a sk ip of 4x in the vertical direction. table 8: subsampling combinations skip y skip x bin x bin xy sum x sum xy 1 1CCCC 2yCyC 4yCyC 2 1CCCy 2yyyy 4yyyy 4 1CCCy 2yyyy 4yyyy 8 1CCCy 2yCyy 4yCyy 16 1CCCy 2yCyy 4yCyy 32 1CCCy 2yCyy 4yCyy
mt9j003-ds rev. e 5/15 en 47 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration frame rate control the frame-time is calculated as the row-time multiplied by the number of rows (frame_length_lines). the row-time is referred to in these calculations as the number of pixel clocks read per row (line_length_pck) multiplied by the vt_pix_clk frequency. the formulas for calculating the frame rate of the mt9j003 are shown below. the line length is programmed in pixel clock periods through the register line_length_pck. the minimum value can be determined as the largest value found in equation 7. these are the required values for either the array readout or the bandwidth available to the parallel or serial interface. absolute minimum array line length pck minimum line_length_pck = min_line_length_pck (see table 9, ?minimum row time and blanking numbers,? on page 48) array readout line length pck (eq 7) interface line length pck (eq 8) (eq 9) note that line_length_pck will be the ma ximum of the three equations. the second equation describes the limitations from the readout of the pixel array while the third determines the frame-rate of the output in terface. the frame-rate using hispi will always be higher than using the parallel in terface. values for min_line_blanking_pck are provided in ?minimum row time? on page 48. the frame length is programmed directly in number of lines in the register frame_line_length. for a specific window si ze, the minimum frame length is shown in equation 10: (eq 10) the frame rate can be calculated from these variables and the pixel clock speed as shown in equation 11: (eq 11) if coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. x_addr_end x_addr_start ? x_odd_inc + 2x x_odd_inc 1 + 2 ------------------ ---------------- - ?? ?? --------------------- ---------------------- --------------------- ----------------- ---------------- min_line_blanking_pck + x_output_size op_pix_clk vt_pix_clk -------------- ----------- - ?? ?? 30 (for parallel) + x_output_size 4 --------------- ----------------- - ?? ?? op_pix_clk vt_pix_clk -------------- ----------- - 30 (for hispi) + minimum frame_length_lines y_addr_end - y_addr_start 1 + subsampling factor -------------------- --------------------- ------------------ ---------------- - min_frame_blanking_lines + ?? ?? = frame rate vt_pixel_clock_mhz x 1 x 10 6 line_length_pck_x frame_length_lines ------------------ ---------------------- ----------------- ------------------ ----------------- - =
mt9j003-ds rev. e 5/15 en 48 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration minimum row time the minimum row time and blanking values with default register settings are shown in tabl e 9. in addition, enough time must be given to the output fifo so it can output all data at the set frequency within one row time. there are therefore three checks that must all be met when programming line_length_pck: 1. line_length_pck> min_line_length_pck in table 9. 2. line_length_pck > 0.5*(x_addr_end - x_addr _start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck in table 9. 3. the row time must allow the fifo to output all data during each row. parallel - line_length_pck > (x_output_si ze) * ?vt_pix_clk period? / ?op_pix_clk period? + 0x005e. hispi (4-lane) - line_length_pck > (1/4)*(x_output_size) * ?vt_pix_clk period? / ?op_pix_clk period? + 0x005e. minimum frame time the minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2). fine integration time limits the limits for the fine_integration_time ca n be found from fine _integration_ time_min and fine_integration_time_max_margin. values for different mode combinations are shown in table 11. fine correction for the fine_integration_time limits, the fine _correction constant will change with the pixel clock speed and binning mode. these values are shown in table 12. table 9: minimum row time and blanking numbers register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 min_line_blanking_pck 0x046e 0x029a 0x01b0 0x0822 0x046c 0x0292 min_line_length_pck 0x0670 0x03e0 0x02f0 0x0cc0 0x0660 0x03d8 table 10: minimum frame time and blanking numbers register min_frame_blanking_lines 0x008f min_frame_length_lines 0x0091 table 11: fine_integration_time limits register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 fine_integration_time_min 0x03f2 0x020a 0x094 0x07b2 0x03ae 0x010c fine_integration_time_max_margin 0x027e 0x012e 0x0108 0x050e 0x0276 0x0224
mt9j003-ds rev. e 5/15 en 49 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration low power mode the mt9j003 sensor supports a low power mode, which can be entered by programming register bit read_mode[9]. setting this bit will do the following: ? double the value of pc_speed[2:0] internal ly. this means halving the internal pixel clock frequency. ? lower currents in the analog domain. this can be done by setting a low power bit in the static control register. the current will be halved where appropriate in the analog domain. note that enabling the low power mode will not put the sensor in subsampling mode. this will have to be programmed separately as described earlier in this document. low power is independent of the readout mode an d can also be enabled in full resolution mode. because the pixel clock speed is halved, the frame rates that can be achieved with low power mode are lower than in full power mode. because only internal pixel clock speeds of 1, 2, and 4 are supported, low power mode combined with pc_speed[2:0] = 4 is an illegal combination. any limitations related to changing the intern al pixel clock speed will also apply to low power mode, because it automatically changes the pixel clock speed. therefore, the limiter registers need to be reprogramme d to match the new internal pixel clock frequency. integration time the integration (exposure) time of the mt9j 003 is controlled by the fine_integration_- time and coarse_integration_time registers. the limits for the fine inte gration time are defined by: fine_integration_time_min < fine_integration_time < (line_length_pck ? (eq 12) fine_integration_time_max_margin the limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (eq 13) the actual integratio n time is given by: (eq 14) it is required that: coarse_integration_time < = (frame_length_lines - coarse_integration_time_max_margin) (eq 15) if this limit is exceeded, the frame time will automatically be extended to ( coarse_inte- gration_time + coarse_integartion_time_max_margin ) to accommodate the larger inte- gration time. table 12: fine_correction values register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 fine_correction 0x09c 0x048 0x01e 0x0134 0x094 0x044 integration_time coarse_integration_time * line_length_pck ?? fine_integration_time + ?? vt_pix_clk_freq_mhz*10 6 ?? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------- =
mt9j003-ds rev. e 5/15 en 50 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration on semiconductor gain model the on semiconductor gain model uses color-specific registers to control both analog and digital gain to the sensor. these registers are: ? global_gain ?greenr_gain ?red_gain ? blue_gain ?greenb_gain the registers provide three 2x and one 4x analog gain stages. the first analog gain stage has a granularity of 64 steps over 2x gain. a digital gain from 1-7x can also be applied. analog gain = (8/(8-g(colamp)<11:9>) x (1 + color_gain[8])(1 + color_gain[7])(color_gain[6:0]/64) (eq 16) bits 11 to 9 are also restricted to 0, 4, and 6. this limits the particular gain stage to 4x. as a result of the different gain stages, anal og gain levels can be achieved in different ways. the recommended gain sequence is shown below in table 13. flash control the mt9j003 supports both xenon and led fl ash through the flash output signal. the timing of the flash signal with the defa ult settings is shown in figure 12, and in figure 13 and figure 14 on page 51. the flash and flash_count registers allow the timing of the flash to be changed. the flash can be programmed to fire only once, delayed by a few frames when asserted, and (for xenon fl ash) the flash duration can be programmed. enabling the led flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. th is can be avoided either by first enabling mask bad frames (write reset_register[9] = 1) before the enabling the flash or by forcing a restart (write reset_register[1] = 1) immediat ely after enabling the flash; the first bad frame will then be masked out, as shown in figure 14 on page 51. read-only bit flash[14] is set during frames that are correctly int egrated; the state of this bit is shown in figures 12, 13, and 14. figure 12: xenon flash enabled table 13: recommended gain stages desired gain recommended gain register setting 1C1.98 0x1040C0x107f 2C3.97 0x1840C0x187f 4C7.94 0x1c40C0x1c7f 8C15.875 0x1cc0C0x1cff 16C31.75 0x1dc0C0x1dff frame_valid flash strobe state of triggered bit (r0x3046-7[14])
mt9j003-ds rev. e 5/15 en 51 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration figure 13: led flash enabled notes: 1. integration time = number of rows in a frame. 2. bad frames will be masked during led flash operation when mask bad frames bit field is set (r0x301a[9] = 1). 3. an option to invert the flash output si gnal through r0x3046[7] is also available. figure 14: led flash enabled following forced restart bad frame frame_valid flash strobe state of triggered bit (r0x3046-7[14]) flash enabled bad frame good frame good frame flash disabled during this frame during this f rame flash enabled masked out good frame good frame flash disabled and a restart frame and a restart triggered triggered frame_valid flash strobe state of triggered bit (r0x3046-7[14]) masked out frame
mt9j003-ds rev. e 5/15 en 52 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration global reset global reset mode allows the integration time of the mt9j003 to be controlled by an external electromechanical shutter. global reset mode is generally used in conjunction with ers mode. the ers mode is used to prov ide viewfinder informat ion, the sensor is switched into global reset mode to captur e a single frame, and the sensor is then returned to ers mode to restore viewfinder operation. overview of global reset sequence the basic elements of the global reset sequence are: 1. by default, the sensor operates in ers mo de and the shutter output signal is low. the electromechanical shutter must be open to allow light to fall on the pixel array. integration time is controlled by the co arse_integration_time and fine_integration_- time registers. 2. a global reset sequence is triggered. 3. all of the rows of the pixel array are placed in reset. 4. all of the rows of the pixel array are taken out of reset simultaneously. all rows start to integrate incident light. the electromechanical shutter may be open or closed at this time. 5. if the electromechanical shutter has been closed, it is opened. 6. after the desired integration time (controlle d internally or externally to the mt9j003), the electromechanical shutter is closed. 7. a single output frame is generated by th e sensor with the usual lv, fv, pixclk, and d out timing. as soon as the output frame ha s completed (fv de-asserts), the electro- mechanical shutter ma y be opened again. 8. the sensor automatically resumes operation in ers mode. this sequence is shown in figure 15. the fo llowing sections expand to show how the timing of this sequ ence is controlled. figure 15: overview of global reset sequence entering and leaving the global reset sequence a global reset sequence can be triggered by a register write to global_seq_trigger[0] (global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suit- ably-configured gpi input (see ?trigger control? on page 36). when a global reset sequence is triggered, the sensor waits for the end of the current row. when lv de-asserts for that row, fv is de-asserted 6 pixclk periods later, potentially truncating the frame that was in progress. the global reset sequence completes with a frame readout. at the end of this readout phase, the sensor automatically resumes op eration in ers mode. the first frame inte- grated with ers will be generated after a delay of approximately: ((13 + coarse_integration_time) * line_length_pck). this sequence is shown in figure 16. ers ers row reset integration readout
mt9j003-ds rev. e 5/15 en 53 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration while operating in ers mode, double-buffered registers are updated at the start of each frame in the usual way. during the global reset sequence, double-buffered registers are updated just before the start of the readout phase. figure 16: entering and leaving a global reset sequence programmable settings the registers global_rst_end and global_read_ start allow the duration of the row reset phase and the integration phase to be controll ed, as shown in figure 17. the duration of the readout phase is determined by the active image size. as soon as the global_rst_end count has expired, all rows in the pixel array are simulta- neously taken out of reset and the pixel array begins to integrate incident light. figure 17: controlling the reset and integr ation phases of the global reset sequence ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start
mt9j003-ds rev. e 5/15 en 54 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration control of the electromechanical shutter figure 18 shows two different ways in which a shutter can be controlled during the global reset sequence. in both cases, the ma ximum integration time is set by the differ- ence between global_read_start and global_rst_end. in shutter example 1, the shutter is open during the initial ers sequence and duri ng the row reset phase. the shutter closes during the integration phase. the pixel array is integrating incident light from the start of the integration phase to the point at wh ich the shutter closes. finally, the shutter opens again after the end of the readout phase. in shutter example 2, the shutter is open during the initial ers sequence and closes sometime during the row reset phase. the shutter both opens and closes during the int egration phase. the pixel array is integrating incident light for the part of the integration phase during which the shutter is open. as for the previous example, the shutter opens again after the end of the readout phase. figure 18: control of the electromechanical shutter it is essential that the shutter remains clos ed during the entire row readout phase (that is, until fv has de-asserted for the frame readou t); otherwise, some rows of data will be corrupted (over-integrated). it is essential that the shutte r closes before the end of the integration phase. if the row readout phase is allowed to start before the shutter closes, each row in turn will be inte- grated for one row-time longer than the previous row. after fv de-asserts to signal the completion of the readout phase, there is a time delay of approximately 10 * line_length_pck before the sensor starts to integrate light-sensitive rows for the next ers frame. it is essential that the shutter be opened at some point in this time window; otherwise, the first er s frame will not be uniformly integrated. the mt9j003 provides a shutter output sign al to control (or help the host system control) the electromechanical shutter. the timing of the shutter output is shown in figure 19 on page 55. shutter is de-asserted by default. the point at which it asserts is controlled by the programming of global_shu tter_start. at the end of the global reset readout phase, shutter de-asserts approximately 2 * line_length_pck after the de- assertion of fv. this programming restriction must be met for correct operation: global_read_start > global_shutter_start ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start maximum integration time shutter open shutter open shutter closed actual integration time shutter open shutter open shutter closed closed shutter open actual integration time shutter example 1 shutter example 2
mt9j003-ds rev. e 5/15 en 55 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration figure 19: controlling the shutter output using flash with global reset if global_seq_trigger[2] = 1 (global flash enabled) when a global reset sequence is trig- gered, the flash output signal will be pulsed during the integration phase of the global reset sequence. the flash output will assert a fixed number of cycles after the start of the integration phase and will remain asserted for a time that is controlled by the value of the flash_count register, as shown in figure 20. figure 20: using flash with global reset external control of integration time if global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is trig- gered, the end of the integration phase is co ntrolled by the level of trigger (global_se- q_trigger[0] or the associated gpi input). this allows the integration time to be controlled directly by an input to the sensor. this operation corresponds to the shutter ?b ? setting on a traditional camera, where ?b? originally stood for ?bulb? (the shutter setting used for synchronization with a magne- sium foil flash bulb) and was later considered to stand for ?brief? (an exposure that was longer than the shutter coul d automatically accommodate). when the trigger is de-asserted to end integrat ion, the integration phase is extended by a further time given by global_read_start ? global_shutter_start . usually this means that global_read_start should be set to global_shutter_start + 1 . the operation of this mode is shown in figure 21 on page 56. the figure shows the global reset sequence being triggered by the gpi2 input, but it could be triggered by any of the gpi inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under software control. ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start shutter global_shutter_start ~2*line_length_pck ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end flash flash_count (fixed)
mt9j003-ds rev. e 5/15 en 56 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration the integration time of the grr sequence is defined as: (eq 17) where: (eq 18) (eq 19) the integration equation allo ws for 24-bit precision when calculating both the shutter and readout of the image. the global_rst_end has only 16-bit as th e array reset function and requires a short amount of time. the integration time can also be scaled using global_scale. the variable can be set to 0?512, 1?2048, 2?128, and 3?32. these programming restrictions must be me t for correct operation of bulb exposures: ? global_read_start > global_shutter_start ? global_shutter_start > global_rst_end ? global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted) figure 21: global reset bulb retriggering the global reset sequence the trigger for the global reset sequence is edge-sensitive; the gl obal reset sequence cannot be retriggered until the global trigger bit (in the global_seq_trigger register) has been returned to ?0,? and the gpi (if any) as sociated with the trigger function has been de-asserted. the earliest time that the glob al reset sequence can be retriggered is the point at which the shutter output de-asserts; this occurs approximately 2 * line_length_pck after the negation of fv for the global reset readout phase. the frame that is read out of the sensor duri ng the global reset readout phase has exactly the same format as any other frame out of th e serial pixel data interface, including the addition of two lines of embedded data. the values of the coarse_integration_time and fine_integration_time registers within the embedded data match the programmed values of those registers and do not reflect the integration time used during the global reset sequence. integration time global _ scale [ global _ read _ start global _ shutter _ start ? global _ rst _ end ] ? ? vt _ pix _ clk _ freq _ mhz ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------- - = global _ read _ start 2 16 global _ read _ start 27:0 ?? ? global _ read _ start 115:0 ?? + ?? = global _ shutter _ start 2 16 global _ shutter _ start 27:0 ?? ? global _ shutter _ start 115:0 ?? + ?? = ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end gpi2 global_read_start - global_shutter_start
mt9j003-ds rev. e 5/15 en 57 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor readout configuration global reset and soft standby if the mode_select[stream] bit is cleared while a global reset sequence is in progress, the mt9j003 will remain in streaming state until the global reset sequence (including frame readout) has completed, as shown in figure 22. figure 22: entering soft standb y during a global reset sequence ers ers row reset integration readout mode_select[streaming] system state software standby streaming
mt9j003-ds rev. e 5/15 en 58 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor core digital data path sensor core digital data path test patterns the mt9j003 supports a number of test patterns to facilitate system debug. test patterns are enabled using test_pattern_mode (r0x0 600?1). the test patterns are listed in tabl e 14 . test patterns 0?3 replace pixel data in the output image (the embedded data rows are still present). test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). hispi test patterns test patterns specific to the hispi are also generated. the test patterns are enabled by using test_enable (r0x31c6 - 7) and controlled by test_mode (r0x31c6[6:4]). for all of the test patterns, the mt9j003 regist ers must be set approp riately to control the frame rate and output timing. this includes: ?all clock divisors ? x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ?line_length_pck ?x_output_size ? y_output_size table 14: test patterns test_pattern_mode description 0 normal operation: no test pattern 1 solid color 2 100% color bars 3fade-to-gray color bars 4 pn9 link integrity pattern (only on sensors with serial interface) 256 walking 1s (12-bit value) 257 walking 1s (10-bit value) 258 walking 1s (8-bit value) table 15: hispi test patterns test_mode description 0 transmit a constant 0 on all enabled data lanes. 1 transmit a constant 1 on all enabled data lanes. 2 transmit a square wave at half the serial data rate on all enabled data lanes. 3 transmit a square wave at the pixel rate on all enabled data lanes. 4 transmit a continuous sequence of pseudo random da ta, with no sav code, copied on all enabled data lanes. 5 replace data from the sensor with a known sequence copied on all enabled data lanes.
mt9j003-ds rev. e 5/15 en 59 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor core digital data path test cursors the mt9j003 supports one horizontal and one ve rtical cursor, allowing a crosshair to be superimposed on the image or on test pa tterns 1?3. the position and width of each cursor are programmable in r0x31e8?r0x31ee. both even and odd cursor positions and widths are supported. each cursor can be inhibited by setting its width to ?0.? the programmed cursor position corresponds to the x and y addresses of the pixel array. for example, setting horizon- tal_cursor_position to the same value as y_add r_start would result in a horizontal cursor being drawn starting on the first row of the image. the cursors are opaque (they replace data from the imaged scene or test pattern). th e color of each cursor is set by the values of the bayer components in the test_data_ red, test_data_greenr, test_data_blue and test_data_greenb registers. as a consequence, the cursors are the same color as test pattern 1 and are therefore invisible when test pattern 1 is selected. when vertical_cursor_position = 0x0fff, the vertical cursor operates in an automatic mode in which its position advances every fram e. in this mode the cursor starts at the column associated with x_addr_start = 0 and advances by a step-size of 8 columns each frame, until it reaches the column associat ed with x_addr_start = 2040, after which it wraps (256 steps). the width and color of the cursor in this automatic mode are controlled in the usual way. the effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the design specification. the behavior of the mt9j003 is shown in figure 23 on page 60 and the test cursors are shown as translucent, for clarity. in prac- tice, they are opaque (they overlay the im aged scene). the manner in which the test cursors are affected by the value of image_ orientation can be understood from these implementation details: ? the test cursors are inserted last in the da ta path, the cursor is applied with out any sensor corrections. ? the drawing of a cursor starts when the pi xel array row or column address is within the address range of cursor start to cursor start + width. ? the cursor is independent of image orientation.
mt9j003-ds rev. e 5/15 en 60 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor sensor core digital data path figure 23: test cursor behavior with image orientation readout direction vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 1 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 1 readout direction readout direction readout direction
mt9j003-ds rev. e 5/15 en 61 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor timing specifications timing specifications power-up sequence the recommended power-up sequence for the mt9j003 is shown in figure 24. the avail- able power supplies?v dd _io, v dd , v dd _tx, v dd _pll, v aa , v aa _pix, v dd _slvs, v dd _slvs_tx ?can be turned on at the same time or have the separation specified below. 1. turn on v dd _io power supply. 2. after 1?500ms, turn on v dd and v dd _tx power supply. 3. after 1?500ms, turn on v dd _pll and v aa /v aa _pix power supplies. 4. after the last power supply is stable, enable extclk. 5. assert reset_bar for at least 1ms. 6. wait 2400 extclks for internal initialization into software standby. 7. configure pll, output, and image settings to desired values 8. set mode_select = 1 (r0x0100). 9. wait 1ms for the pll to lock before streaming state is reached. figure 24: power-up sequence note: digital supplies must be turned on before analog supplies. table 16: power-up sequence definition symbol min typ max unit v dd _io to v dd , v dd _tx time t 10C500ms v dd , v dd _tx to v dd _pll time t 20C500ms v dd , v dd _tx to v aa /v aa _pix time t 30C500ms v aa , v aa _pix to v dd _slvs_tx t 4CC500ms active hard reset t 5 1CC ms internal initialization t 6 2400 C C extclks pll lock time t 7 1CC ms internal init hard reset software standby pll lock streaming t 1 t 2 t 3 t 5 t 6 t 7 v dd_ slvs_tx t 4 v aa , vaa_pix extclk v dd _pll v dd, v dd_ slvs, v dd_ tx v dd_ io reset_bar
mt9j003-ds rev. e 5/15 en 62 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor timing specifications power-down sequence the recommended power-down sequence for the mt9j003 is shown in figure 25. the available power supplies?v dd _io, v dd , v dd _tx0, v dd _pll, v aa , v aa _pix, v dd _slvs, v dd _slvs_tx?can be turned off at the same time or have the separation specified below. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert hard reset by setti ng reset_bar to a logic ?0.? 4. turn off the v aa /v aa _pix and v dd _pll power supplies. 5. after 1 ? 500ms, turn off v dd and v dd _tx0 power supply. 6. after 1 ? 500ms, turn off v dd _io power supply. figure 25: power-down sequence table 17: power-down sequence definition symbol min typ max unit hard reset t 1 1CC ms v dd _slvs_tx to v dd time t 20C500ms v dd /v aa /v aa _pix to v dd time t 30C500ms v dd _pll to v dd time t 40C500ms v dd to v dd _io time t 50C500ms t 5 t 4 t 3 v dd _ io v dd , v dd _ tx, v dd _slvs v dd _pll v aa , vaa_pix v dd _slvs_tx extclk reset_bar turning off power supplies hard reset software standby streaming t 1 t 2
mt9j003-ds rev. e 5/15 en 63 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor timing specifications hard standby and hard reset the hard standby state is reached by the as sertion of the reset_bar pad (hard reset). register values are not retained by this action, and will be returned to their default values once hard reset is completed. the minimum power consumption is achieved by the hard standby state. the details of the sequence are described below and shown in figure 26 on page 63. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert reset_bar (active low) to reset the sensor. 4. the sensor remains in hard standby state if reset_bar remains in the logic ?0? state. figure 26: hard standby and hard reset extclk mode_select r0x0100 reset_bar logic 1 logic 0 streaming soft standby hard standby from hard reset next row/frame
mt9j003-ds rev. e 5/15 en 64 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor timing specifications soft standby and soft reset the mt9j003 can reduce power consumption by switching to the soft standby state when the output is not needed. register valu es are retained in the soft standby state. once this state is reached, soft reset can be enabled optionally to return all register values back to the default. the details of the sequence are described below and shown in figure 27. soft standby 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. soft reset 1. follow the soft standby sequence listed above. 2. set software_reset = 1 (r0x0103) to start the internal initialization sequence. 3. after 2400 extclks, the internal initializa tion sequence is completed and the current state returns to soft standby automatically. all registers, including software_reset, return to their default values. figure 27: soft standby and soft reset extclk mode_select r0x0100 software_reset r0x0103 logic 1 logic 0 streaming soft s tandby soft reset soft standby next row/frame logic 0 logic 1 logic 0 2400 extclks logic 0 logic 0 logic 0
mt9j003-ds rev. e 5/15 en 65 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor spectral characteristics spectral characteristics figure 28: quantum efficiency 0 5 10 15 20 25 30 35 40 45 50 350 400 450 500 550 600 650 700 750 blue green red quantum efficiency (%) wavelength (nm)
mt9j003-ds rev. e 5/15 en 66 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor spectral characteristics table 18: cra (13.4) image height cra % mm deg 00 0 50.191 0.67 10 0.382 1.34 15 0.574 2.01 20 0.765 2.68 25 0.956 3.35 30 1.147 4.03 35 1.339 4.70 40 1.530 5.37 45 1.721 6.04 50 1.912 6.71 55 2.103 7.38 60 2.295 8.05 65 2.486 8.72 70 2.677 9.39 75 2.868 10.06 80 3.059 10.73 85 3.251 11.41 90 3.442 12.08 95 3.633 12.75 100 3.824 13.42 0 2 4 6 8 10 12 14 16 18 20 0 102030405060708090100110 cra (deg) image height (%)
mt9j003-ds rev. e 5/15 en 67 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics electrical characteristics caution stresses greater than those listed in table 20 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. notes: 1. exposure to absolute maximum rating cond itions for extended periods may affect reliability. table 19: dc electrical defi nitions and characteristics f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.8v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0, 10mp frame-rate at 14.7 fps definition condition symbol min typ max unit core digital voltage v dd 1.7 1.8 1.9 v i/o digital voltage parallel pixel data interface v dd _io 1.7 1.8 1.9 v analog voltage v aa 2.4 2.8 3.1 v pixel supply voltage v aa _pix 2.4 2.8 3.1 v pll supply voltage v dd _pll 2.4 2.8 3.1 v hispi digital voltage v dd _slvs 1.7 1.8 1.9 v hispi i/o digital voltage v dd _slvs_tx 0.3 0.4 0.9 v digital operating current streaming, full resolution 35 41 45 ma i/o digital operating current streaming, full resolution 0 0 0 ma analog operating current streaming, full resolution 132 169 190 ma pixel supply current streaming, full resolution 2.7 7.6 13.3 ma pll supply current streaming, full resolution 6.5 7 7.5 ma hispi digital operating current streaming, full resolution n/a 20 n/a ma hispi i/o digital operating current streaming, full resolution 13 13.5 14 ma soft standby (clock on) 1.3 1.5 1.9 mw table 20: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 1.9 v v dd _io_max i/o digital voltage C0.3 3.1 v v aa _max analog voltage C0.3 3.5 v v aa _pix pixel supply voltage C0.3 3.5 v v dd _pll pll supply voltage C0.3 3.5 v v dd _slvs_max hispi digital voltage C0.3 1.9 v v dd _slvs_tx_max hispi i/o digital voltage C0.3 1.2 v i dd digital operating current C 90 ma i dd _io i/o digital operating current C 100 ma i aa _max analog operating current C 225 ma i aa _pix pixel supply current C 6 25 ma i dd _pll pll supply current C 25 ma t op operating temperature measure at junction C30 70 c t st storage temperature C40 85 c
mt9j003-ds rev. e 5/15 en 68 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics 2. to keep dark current and shot noise artifacts from impacting image quality, care should be taken to keep t op at a minimum. note: monitor is a low power vga preview mode. the power consumption values in this table represent a small sample of mt9j003 sensors. the i dd io current will double if the v dd _io voltage is raised to 2.8v. figure 29: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 21: parallel interface configured to use low power mode f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; tj = 60c; parallel data rate = 80mp/s frame rate i aa i ddpll i dd i ddio ia apix 10mp 7.5 fps 103.29 10.26 23.93 11.53 2.33 388 mw 720p60 59.94 fps 122.78 10.25 23.85 11.21 5.39 451 mw 1080p30 29.97 fps 114.67 10.26 22.89 4.49 4.14 411 mw vga60 59.94 fps 82.66 10.27 18.5 4.51 5.25 316 mw monitor 29.97 fps 69.22 10.28 16.3 6.35 2.76 271 mw table 22: two-wire serial register interface electrical characteristics f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 symbol parameter condition min typ max unit v il input low voltage C0.5 0.73 0.3 x v dd _io v i in input leakage current no pull up resistor; v in = v dd _io or d gnd C2 2 ? a v ol output low voltage at specified 2 ma 0.031 0.032 0.035 v s data s clk write start ack stop s data s clk read start ack tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% t sdh t sds t shaw t ahsw t stps t stph register address bit 7 write address bit 0 register value bit 0 register value bit 7 read address bit 0 register value bit 0 write address bit 7 read address bit 7 t shar t sdsr t sdhr t ahsr t srth t sclk
mt9j003-ds rev. e 5/15 en 69 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics table 23: two-wire serial register interface timing specification f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 i ol output low current at specified v ol 0.1v 3 ma c in input pad capacitance 6 pf c load load capacitance pf symbol parameter condition min typ max unit f sclk serial interface input clock C 0 100 400 khz sclk duty cycle v od 45 50 60 % t rsclk/s data rise time 300 ? s t srts start setup time master write to slave 0.6 ? s t srth start hold time master write to slave 0.4 ? s t sdh s data hold master write to slave 0.3 0.65 ? s t sds s data setup master write to slave 0.3 ? s t shaw s data hold to ack master read to slave 0.15 0.65 ? s t ahsw ack hold to s data master write to slave 0.15 0.70 ? s t stps stop setup time master write to slave 0.3 ? s t stph stop hold time master write to slave 0.6 ? s t shar s data hold to ack master write to slave 0.3 1.65 ? s t ahsr ack hold to s data master write to slave 0.3 0.65 ? s t sdhr s data hold master read from slave .012 0.70 ? s t sdsr s data setup master read from slave 0.3 ? s table 22: two-wire serial register interf ace electrical characteristics (continued) f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 symbol parameter condition min typ max unit
mt9j003-ds rev. e 5/15 en 70 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics figure 30: i/o timing diagram table 24: i/o parameters f extclk = 15 mhz; v dd = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 symbol definition conditions min max units v ih input high voltage v dd _io = 1.8v 1.4 v dd _io + 0.3 v v dd _io = 2.8v 2.4 v il input low voltage v dd _io = 1.8v gnd C 0.3 0.4 v dd _io = 2.8v gnd C 0.3 0.8 i in input leakage current no pull-up resistor; v in = v dd or d gnd C 20 20 ? a v oh output high voltage at specified i oh v dd _io - 0.4v C v v ol output low voltage at specified i ol C0.4v i oh output high current at specified v oh CC12ma i ol output low current at specified v ol C9ma i oz tri-state output leakage current C10 ? a table 25: i/o timing f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 symbol definition conditions min typ max units f extclk input clock frequency pll enabled 6 24 48 mhz t extclk input clock period pll enabled 166 41 20 ns t r input clock rise time 0.1 C 1 v/ns t f input clock fall time 0.1 C 1 v/ns data[11:0] frame_valid/ line_valid frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. pixclk extclk t cp t r t extclk t f t rp t fp t pd t pd t pfh t plh t pfl t pll pxl _0 pxl _1 pxl _2 pxl _n 90% 10% 90% 10%
mt9j003-ds rev. e 5/15 en 71 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics clock duty cycle 45 50 55 % t jitter input clock jitter C C 0.3 ns output pin slew fastest c load = 15pf C 0.7 C v/ns f pixclk pixclk frequency default C 80 C mhz t pd pixclk to data valid default C C 3 ns t pfh pixclk to frame_valid high default C C 3 ns t plh pixclk to line_valid high default C C 3 ns t pfl pixclk to frame_valid low default C C 3 ns t pll pixclk to line_valid low default C C 3 ns table 25: i/o timing f extclk = 15 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _slvs = 1.8v, v dd _slvs_tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 480 mhz,; dll set to 0 symbol definition conditions min typ max units
mt9j003-ds rev. e 5/15 en 72 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics figure 31: hispi eye diagram for both clock and data signals table 26: hispi rise and fall times at 480 mhz measurement conditions: phy supply 1.8v, hispi powe r supply 0.8v, data rate 480mhz, dll set to 0 parameter name value unit max setup time from transmitter txpre 0.44 ui max hold time from transmitter txpost 0.44 ui rise time t t rise 350 ps fall time t t fall 350 ps output impedance 66 ? table 27: hispi rise and fall times at 360 mhz measurement conditions: phy supply 1.8v, hispi powe r supply 0.8v, data rate 480mhz, dll set to 0 parameter name value unit max setup time from transmitter txpre 0.48 ui max hold time from transmitter txpost 0.42 ui rise time t t rise 350 ps fall time t t fall 350 ps output impedance 66 ? clkjitter trigger/reference vdiff max vdiff ui/2 ui/2 vdiff txpre txpost clock mask data mask t rise t fall 20% 80%
mt9j003-ds rev. e 5/15 en 73 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor electrical characteristics figure 32: hispi skew between data signals within the phy note: the clock dll steps 6 and 7 are not recommen ded by on semiconductor for the mt9j003 rev. 2. note: the data dll steps 3, 5, and 7 are not recomm ended by on semiconductor for the mt9j003 rev. 2. table 28: channel, phy and intra-phy skew measurement conditions: phy supply 1.8v, hispi powe r supply 0.8v, data rate 480mhz, dll set to zero data lane skew in reference to clock tchskew1phy -150 ps table 29: clock dll steps measurement conditions: phy supply 1.8v, hispi power supply 0.8v, data dll set to zero clock dll step 1 2 3 4 5 step delay @ 480mhz 0.25 0.375 0.5 0.625 0.75 ui eye_opening@ 480 mhz 0 .85 0.78 0.71 0.71 0.69 ui eye_opening@ 360 mhz 0 .89 0.83 0.81 0.60 046 ui table 30: data dll steps measurement conditions: phy supply 1.8v, hispi power supply 0.8v, clock dll set to 0 data dll step 1 2 4 6 step delay @ 480mhz 0.25 0.375 0.625 0.875 ui eye opening@ 480 mh z 0.79 0.84 0.71 0.61 ui eye opening@ 360 mh z 0.85 0.83 0.82 0.77 ui tchskew1phy
mt9j003-ds rev. e 5/15 en 74 ?semiconductor components industries, llc,2015 mt9j003: 1/2.3-inch 10 mp cmos digital image sensor package dimensions package dimensions figure 33: 48-pin ilcc package outline drawing notes: 1. dimensions in mm. dimensions in () are for reference only. 2. encapsulant: epoxy 3. substrate material: plastic laminate 0.5 thickness 4. list material: borosilicate glass 0.4 thickness. refrac tive index at 20c = 1.5255 @ 546nm and 1.5231 @ 588nm. 5. lead finish: gold plating, 0.5 microns minimum thickness. 6. image sensor die 0.2 thickness. 7. maximum rotation of optical area relative to seating plane a: 25 microns. maximum tilt of optical area relative to top of cover glass: 20 microns. maximum tilt of optical area relative to top of cover glass: 50 microns. 8. die center = package center; optical center offset from package center: x = 0.01356, y = -0.081705 (0, 2) (1, 25) 1.40.5 0.7250.075 100.075 5.0820.075 5.0140.075 100.075 47x 0.80.05 48x 0.40.05 0.5250.05 7.50.10 ctr optical center 8 optical area 7 first clear pixel (4.589 ctr) (6.413 ctr) (0.125) encapsulant 2 substrate 3 lid 4 image sensor die 6 3.85 0.7 typ. 7.7 7.7 3.85 4.5 9 0.7 typ. 4.2 4.5 80.10 ctr section a - a seating plane a 0.1 a 0.1 a c a 0.15 c b a 0.15 c b a 0.15 c b
mt9j003-ds rev. e 5/15 en 75 ?semiconductor components industries, llc,2015 mt9j003: 1/2.3-inch 10 mp cmos digital image sensor package dimensions figure 34: 48-pin tplcc package outline drawing top view (see-through) capture direction with lens die pad 1 first clear pixel primary datum sensor center side view housing substrate glass 8.000.05 ?0.60 0.00 -0.03 4.000.1 ?0.60 0.00 -0.03 4.000.1 8.000.05 ?0.55 0.00 -0.03 3 - 0.050.05 3 - 0.650.05 8.000.05 8.200.05 10.300.05 7.200.05 10.300.05 6.400.05 6.200.05 1.350.15 0.300.05 1.050.10 4 - 0.41 4 - 0.30 0.250.05 0.550.1 0.850.1 3 - ?1.60 3 - ?1.85 b b b b 4 -r0.30 b 120.075 1.40.05 120.075 3.85 7.7 0.7 typ. 0.7 typ. 3.85 7.7 48*0.40.05 47*0.80.05 1 48 4.2 4.5 4.5 bottom view 1 48 9.0 notes: 1. die thickness: 203 mm typ. 2. gloss thickness: 300mm typ. 3. pcb thickness: 300 mm typ. 4. tilt of sensor relative to substrate: 0.3 max. 5. tilt of sensor optical area relative t o three seating pads located on the sensor housing: 0.7 max. 6. rot ation of sensor optical area relative to the two of the horizontally located f0.60 pins: 1.0 max. 7. optical ce nt er offset from housing cente r: 100mm max. 8. optical ce nt er = pack age ce nter = housing cente r
mt9j003-ds rev. e 5/15 en 76 ?semiconductor components industries, llc,2015. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor package dimensions table 31: 48-pin tplcc pin assignment pin number name pin number name pin number name 1 slvsc_n 17 test 33 atest1_btm 2 slvs_1_p 18 reset_bar 34 atest2_btm 3slvs_1_n19 v dd 35 v aa _pix 4slvs_0_p20gnd36v aa _pix 5slvs_0_n21v dd _io 37 pix gnd 6v dd _slvs_tx 22 gpi0 38 v aa 7v dd _slvs 23 gpi1 39 atest2_top 8v dd _io 24 gpi2 40 atest1_top 9 gnd 25 gpi3 41 v aa 10 v dd 26 shutter 42 a gnd 11 extclk 27 flash 43 gnd 12 v dd 28 gnd 44 slvs3_p 13 gnd 29 v dd _pll 45 slvs3_n 14 v dd _io 30 v pp 46 slvs2_p 15 s data 31 a gnd 47 slvs2_n 16 s clk 32 v aa 48 slvsc_p
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9j003: 1/2.3-inch 10 mp cmos digital image sensor revision history mt9j003-ds rev. e 5/15 en 77 ?semiconductor components industries, llc,2015 . revision history rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/15 ? updated ?ordering information? on page 2 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/26/15 ? converted to on semiconductor template ? removed confidential marking rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/10/12 ? updated trademarks ? updated section on ?pll? on page 37 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/18/10 ? updated table 2, ?available part numbers,? on page 2 ? updated table 1, ?key performance parameters,? on page 1 ? added table 18, ?cra (13.4),? on page 66 ? updated figure 33: ?48-pin ilcc package outline drawing,? on page 74 ? added figure 34: ?48-pin tplcc package outline drawing,? on page 75 ? added table 31, ?48-pin tplcc pin assignment,? on page 76 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/25/09 ?initial release

▲Up To Search▲

Price & Availability of MT9J003D00STMUC2CBC1-200

	To Download MT9J003D00STMUC2CBC1-200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .